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 name    opcodes   description
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 CPUID   0F A2     CPU identification
                   in:   EAX=0         get max. identification level and vendor
                   out:  EAX=1         max. identification level is 1 now
                         EBX-EDX-ECX   vendor identification
                           'GenuineIntel' - Intel i486, iPentium or iP6 CPU
                           'UMC UMC UMC ' - UMC U5S or U5D processor
                           'AuthenticAMD' - AMD 486DX2 or DX4 (enh.) processor
                           'CyrixInstead' - Cyrix M1 processor
                   in:   EAX=1         get chip type and the supported features
                   out:  EAX=0:TFMS    CPU type (type, family, model, stepping)
                           type        The type is encoded in the bits13/12.
                                       00=1st dual iPentium CPU (iP54C)
                                       01=iPentium OverDrive processor
                                       10=2nd dual iPentium CPU (iP54C)
                                       11=reserved
                           family      4=486, 5=iPentium, 6=iP6
                           model       Intel486: 0=DX, 1=DX50, 2=SX, 3=DX2,
                                                 4=SL, 5=SX2, 7=DX2WB, 8=DX4
                                       UMC486:   1=U5D, 2=U5S
                                       AMD486:   3=DX2, 7=DX2WB, 8=DX4, 9=DX4WB
                                       iPentium: 0=5V-60/66 MHz A-step chips,
                                                 1=5V-60/66 MHz, 2=3.3V-75/90/
                                                 100/120/133MHz, 3=P24T, 4=OvDr
                                                 for iPentium-3.3V, 5=OvDr for
                                                 iDX4, 6=OvDr for iPentium-5V
                                       iP6:      4=P55CT (iPentium-3.3V OvDr)
                           stepping    steppings sometimes cover several masks
                           comment     iPentium-5V: no fDIVbug since step no.7
                                       iPentium-3V: no fDIVbug since step no.4
                         EDX=flags     supported features (i486, iPentium, iP6)
                           bit31..10   reserved (=0)
                           bit9=1      CPU contains a local APIC (iPentium-3V)
                           bit8=1      CMPXCHG8B instruction supported
                           bit7=1      machine check exception supported
                           bit6=0      reserved (36bit-addressing & 2MB-paging)
                           bit5=1      iPentium-style MSRs supported
                           bit4=1      time stamp counter TSC supported
                           bit3=1      page size extensions supported
                           bit2=1      I/O breakpoints supported
                           bit1=1      enhanced virtual 8086 mode supported
                           bit0=1      CPU contains a floating-point unit (FPU)
                   info: can be used in all CPLs; serializes the pipelines; the
                         first iPentiums did not supported several CPUID levels
                         and they show EAX=FMS and EBX-EDX-ECX=vendor only! (so
                         they seem to provide more than 500h CPUID levels)
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 RDMSR   0F 32     read a model specific register value
                   in:   ECX      number of the MSR (0..13h on the iPentium)
                   out:  EDX:EAX  value of the MSR (64 bit wide)
                   clks: 20-24 (iPentium)
                   info: instruction can only be used when CPL=0 (but many EMMs
                         do allow the usage from CPL>0 without problems; if the
                         instruction is used in a Windows 3.1 DOS-box, then the
                         DOS-session will be 'crashed' due to an opcode error)
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 WRMSR   0F 30     write a value to a model specific register
                   in:   ECX      number of the MSR (0..13h on the iPentium)
                         EDX:EAX  value (64 bit wide)
                   clks: 30-45 (iPentium)
                   info: instruction can only be used when CPL=0 (but some EMMs
                         like QEMM 7.04 do allow the usage from CPL>0)
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 RDTSC   0F 31     read time stamp counter value
                   out:  EDX:EAX  time stamp counter value (64 bit wide)
                   clks: 6 (iPentium, CPL=0), 11 (iPentium, CPL=1-3)
                   info: instruction can be disabled for CPL=1..3 via CR4.TSD
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 CMPXCH8B      0F C7      compare & exchange 64 bits, similar to CMPXCHG
 RSM           0F AA      resume from system management mode (only in SMM!)
 MOV EAX,CR4   0F 20 E0   read the CR4 register value
 MOV CR4,EAX   0F 22 E0   write a value to the CR4 register
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 The MOV EAX,TRxh and MOV TRxh,EAX instructions are not longer supported by the
 iPentium processors, because the Test Registers were placed into the MSRs.

